In modern semiconductor manufacturing, reliability of good die and semiconductor devices is critically important. In packaging semiconductor die, a 100% reliability is optimal. Currently, one common technique of packaging a semiconductor die is to flip-chip join a semiconductor die to a ceramic substrate. According to this technique, the active surface of the semiconductor die is "bumped", and the bumps are reflowed while in contact with an array of solder pads on a substrate to provide electrical and mechanical interconnection. Electrical traces extend through the substrate to an opposing major surface thereof, the electrical traces being routed to an array of solder pads which are spaced apart from each other on a much larger scale than the bumps of the die. This known technique is illustrated in FIGS. 1 to 4.
FIG. 1 illustrates a conventional structure including a semiconductor die 10 attached to a ceramic substrate 14 by a plurality of bumps 12. As shown, the ceramic substrate 14 has a plurality of solder pads 16, as are well known in the art. Bumps 12 are generally formed by the known "controlled collapse chip connection" technology, alternatively known as C4 technology. After bumps 12 are formed on semiconductor die 10, they are reflowed at a relatively high temperature, such as 360.degree. C., to form an electrical and mechanical interconnect between the semiconductor die and the ceramic substrate 14. The C4 bumps are generally formed of a high lead solder, such as 90 Pb/10 Sn (90% Pb, 10% Sn). Then, as shown in FIG. 2, a plurality of solder spheres 22 are placed in a conventional graphite boat, which provides a carrier for the solder spheres 22. Like the solder of bumps 12, solder spheres 22 are also formed of a high lead solder.
A solder paste 24 is then screen-printed over the solder spheres 22 provided in the graphite boat, and the ceramic substrate 14 and the solder spheres 22 are joined. Particularly, the solder paste 24 is comprised of flux and a low melting temperature solder component, such as 63 Sn/37 Pb. To effect joining of the solder spheres to the solder pads 16 of substrate 14, heating is carried out at a temperature on the order of 210.degree. C. After heating, a final package is shown in FIG. 4, which, in this particular embodiment, forms a ceramic ball grid array 26.
With increasing I/O densities of the die, larger substrates are typically required. For example, 21 by 21 millimeter and 25 by 25 millimeter ceramic substrates are currently utilized in production. However, due to the ever increasing I/O count of the semiconductor die, it would be desirable to utilize a larger substrate, such as on the order of 32 by 32 millimeter, and 35 by 35 millimeter. However, such large-sized substrates are generally difficult to employ, because of the thermal expansion coefficient mismatch between the substrate and the printed circuit board. As the size of the ceramic substrate increases, this difference in degree of thermal expansion becomes more problematic due to the higher shear strain generated between the ceramic substrate and the printed circuit board during heat cycling.
In addition, it is also a goal to eliminate as many packaging components and process steps as possible, with an ultimate objective of achieving direct semiconductor die to printed circuit board connection. However, such a direct connection is not pragmatic in view of the large differences in thermal expansion coefficients. Such a mismatch requires an underfill provided between the semiconductor die and the printed circuit board, the underfill providing matching thermal expansion characteristics to prevent interconnect fatigue and maintain the electrical and mechanical integrity of the interconnects. Such an underfill material is difficult to incorporate in current manufacturing practices. For example, an assembler of electronic equipment can no longer simply solder a semiconductor device into place on a circuit board, but rather, must employ additional underfill steps, requiring extensive curing times, thus negatively impacting through-put.
Accordingly, it is well understood that improved electrical interconnections, both first-level and second-level packaging interconnections, are desirable and needed in the art.